HBM Test Standards

• Test Standards

• EIA/JEDEC JESD22-A114-F

• ESD-STM5.1 200

The Human Body Model is a situation where a certain amount of energy from an external electrical power or an electrostatic energy source becomes charged within the human body and then discharged as electrostatic energy. A common example of this occurrence is when a person accumulates static charge by walking across a carpet and then transferring all of the charge to a device by touching it.

CDM

Test Standards

• EIA/JEDEC JESD22-C101 F

• ESD-DS5.3.1 1999

There are currently two widely-used models for CDM testing: 

1. Socketed Discharge Model (SDM) – SDM simulates a device inserted in a socket, then charged from a high voltage source, and then discharged through a 1-ohm resistor. SDM is easy to conduct but is not always replicating real-world CDM ESD events.
2. Real-world Charged Device Model (RCDM) – RCDM testing consists of putting the DUT in dead-bug position on a thin dielectric (FR4), which is then placed over a ground plate. The DUT is then charged either directly by a charging probe or indirectly by field induction. Each pin is then discharged through a 1-ohm resistor to ground.

MM

• Test Standards

• EIA/JEDEC JESD22-A115-C

• ESD-STM5.2 1999

The Machine Model is a situation where electrostatic energy is charged within the machine through a grounding problem or some other negative influence. The MM simulates a more rapid and severe electrostatic discharge from a charged machine, fixture, or tool. The MM test circuit consists of charging up a 200-pF capacitor to a certain voltage and then discharging this capacitor directly into the device being tested through a 500 NH inductor with no series resistor.

LU

• Test Standards

• EIA/JEDEC JESD78 D; TLP (Transmission Line Pulse Model)

The purpose of Latch Up testing is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability. The latch-up test is used with CMOS processes to detect a state in which a low-impedance path, resulting from an overstress that triggers a parasitic Thyristor structure like, persists after removal of the triggering condition.