ACCELERATING YOUR TIME TO MARKET WITH ISS INNOVATIVE ENGINEERING EXPERTISE

Integrated Semiconductor Solutions, Inc. (ISS) provides a complete range of semiconductor processes, products, package qualifications and all reliability stress tests solutions and engineering services for (IDM) Integrated Device Manufacturers.

ISS facilitates production level burn-in and all other services for fast ramping to volume manufacturing 24 hours a day, 7 days a week.

Highest Quality and most reliable systems & products
Reduce unit costs for fabless and start-up Integrated Device manufacturers
Over 20+ years of technical expertise
Extensive industry exposure utilizing our (IDM) specialization

We work closely with our customers to design, develop, test, analyze, and debug the most challenging projects.

ISS Philosophy and Vision

ISS has been providing High Quality Reliability Testing services for fabless and start-up Integrated Device manufacturers. Our goal is to meet all Customer Requirements and deliver the highest quality services and Solutions to all technical challenges. We are passionate and provide friendly, customer service and complete satisfaction.

ESD, MM, CDM and Latch-Up Testing Services
Product & Process Reliability Testing Services
Package Qualification Services
PCB Design Fab & Assembly Services
Customize Burn-In Board Design
Customize ESD Board Design

Additional Services Provided by ISS

Failure Analysis Services
ATE / Test Programming / Test Development / ATE Testing Support
IN-HOUSE Production Burn-In with competitive overseas pricing in the US (You Save US customs and shipping costs)

COMPANY PROFILE

ISS Inc. is a Cooperation registered in the state of California. Our Reliability Stress test service laboratory is dedicated to provide customers outmost engineering support 24 hours 7 days a week. Since ISS engineering staff is experienced in the Semiconductor Device Manufacturing industry provides solutions to any technical challenges. Whether Semiconductor Company having issues ranging from board design, packages, down through the single devices level, Pattern conversions, our dedicated team work closely to resolve and get the projects started and ACCELERATE TIME TO MARKET.

Providing full turnkey solutions.
Optional selections of any services.

FULL TURNKEY TEST SERVICES AND ONE SHOP STOP SOLUTIONS WITH ISS

Hardware Design

Hardware Debug

Burn-in Services

ESD/CDM testing

Package Qualification

ATE Testing

Online Brochure : A copy can be downloaded from this link: ISS eBrochure

Test Services

ISS ESD & Environmental Testing lab has the equipment Engineering expertise over 25 years of experience to support in-house full test and diagnostic solutions.

IC Qualifications For ESD
ESD Testing Services Offered
- Human Body Model Testing (HBM)
- Machine Model Testing (MM)
- Charged Device Model Testing (CDM)
- Latch-Up Testing (LU)
- Methodology latest industry standard
Burn-in Product, Process, Reliability Qualification Capability and Capacities
ISS services are capable of providing cost effective and economical solutions with existing integration solution for all Burn-in needs.
- HTOL (High Temp Operating Life)
- Dynamic HTOL with thermal runaway control
- Early Lifetime Failure
- Intelligent Life Test (test while burn-in)
- Burn-in Chambers (with complete scalable positions)
- Burn-in Test Program & 1st Article Test
- Adaptation to most common burn-in configurations and power requirements
Device Package Qualification Services Pre and Post (Preconditioning) Tests Includes
- PRE-CSAM - CSAM testing to confirm if any Delamination or other anomalies exist prior to Pre-Conditioning
- Bake Oven - 24 hours bake to drive out any pre-existing moisture
- Moisture Soak - As required by the customer
- Solder Reflow - 3 cycles of solder reflow process
- POST-CSAM - CSAM testing again to determine if any delamination occurred during the test.
- Bias or Unbiased Highly Accelerated Stress Test (HAST)
- Temperature Cycling (TCY)
- High Temperature Storage (HTS)
- Bias, Un Biased or Dynamic 85/85 stress testing (THB)

IC Package Failure Analysis
- Level 1/2/3 IC Failure Analysis
- Backside IC Editing Services
- PCB Failure Analysis
- Electrical Characterizaion | Microprobing
- High-Pin Count Parametric Testing
- CHemical Mechanical Decapsulation
- DIon Cross Section Milling, Polishing, and Cutting
- 3D CT sub-micron X-RAY Analysis
- Solder Joint Integrity
- CSAM Evaluation
- High-Resolution IC Photo Navigation
- IC Process Evaluation | Documentation
- IR|XIVA|TIVA|Obirch Analysis
- Photon Emission Microscopy
- Temperature Mapping
- Precise Chemical | Mechanical Deprocessing
- Rie Passivation | Dielectric Removal
- Precise Sub-Micron Cross-Sectioning
- Precise Substrate Thinning | Polishing
- SEM Analysis and Imaging
- EDS EDAX Analysis
- Focused Ion Beam FIB IC Circuit Modifications
- DUAL-BEAM FIB Services
- DUAL-BEAM Focused Ion Beam FIB Nano-Fabrication
- Electronic Component DPA
- DYE and PRY
Engineering and Hardware Capabilities
ISS offer Complete Turnkey Solutions for PCBs Design, Fabrication, Assembly and Testing.?ISS have highly experienced design team to provide high level designs for all applications matching impedance for high speed differential signal multi layers with maximum densities to fine pitch designs. Currently Supported PCB?€™s by ISS:
- HTOL Burn-In Boards for all systems
- HAST Boards
- ATE Load Boards
- ESD test Fixtures
- Programmable Module PCB
- Any types of Adaptors for Bench Testing
- Customize Burn-In Oven System Back Planes

Test Capabilities

ISS currently has equipment on hand for complete Reliability Support for Low and High Power Products, ESD Characterization and Testing Plans for High Pin count and Supply Count and all required stress tests for all product, process and package Qualification.

System supports HBM, MM, and Latch Up testing

System supports CDM testing

Burn-in Product, Process, Reliability Qualification Capability and Capacities
Mid power range MCC ABES-IV
- Up to 128 individual free programmable I/O channel
- Up to 5 power supplies, and 2MB vector
- Up to 2 zones individual temperatures
REL In Cal 160 Fully Dynamic Burn-In
- Up to 160 programmable I/O channels
- Up to 6 zones with 48 slots
- Up to individual driver drive 8 slots
Criteria (XXV) C25 6 zones, 48 slots / each Burn-in Systems (Capacity Available 8 ovens) for Mass productions.
- Up to 4M vector depth, configurable from 48-96 channel
Individual Burn-in Systems for:
- Individual custom temperature and power supplies setting for device specification.
- Up to 4M vector depth, configurable from 48-96 channels

Test Standards

ISS offers a full line of component qualification process for ESD testing to JEDEC and ESDA standards.

HBM Test Standards
- Test Standards
- EIA/JEDEC JESD22-A114-F
- ESD-STM5.1 200
The Human Body Model is a situation where a certain amount of energy from an external electrical power or an electrostatic energy source becomes charged within the human body and then discharged as electrostatic energy. A common example of this occurrence is when a person accumulates static charge by walking across a carpet and then transferring all of the charge to a device by touching it.
CDM
Test Standards
- EIA/JEDEC JESD22-C101 F
- ESD-DS5.3.1 1999
There are currently two widely-used models for CDM testing: (BOLD)

1. Socketed Discharge Model (SDM) - SDM simulates a device inserted in a socket, then charged from a high voltage source, and then discharged through a 1-ohm resistor. SDM is easy to conduct but is not always replicating real-world CDM ESD events.

2. Real-world Charged Device Model (RCDM) - RCDM testing consists of putting the DUT in dead-bug position on a thin dielectric (FR4), which is then placed over a ground plate. The DUT is then charged either directly by a charging probe or indirectly by field induction. Each pin is then discharged through a 1-ohm resistor to ground.
MM
- Test Standards
- EIA/JEDEC JESD22-A115-C
- ESD-STM5.2 1999
The Machine Model is a situation where electrostatic energy is charged within the machine through a grounding problem or some other negative influence. The MM simulates a more rapid and severe electrostatic discharge from a charged machine, fixture, or tool. The MM test circuit consists of charging up a 200-pF capacitor to a certain voltage and then discharging this capacitor directly into the device being tested through a 500 NH inductor with no series resistor.
LU
- Test Standards
- EIA/JEDEC JESD78 D; TLP (Transmission Line Pulse Model)
The purpose of Latch Up testing is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability. The latch-up test is used with CMOS processes to detect a state in which a low-impedance path, resulting from an overstress that triggers a parasitic Thyristor structure like, persists after removal of the triggering condition.
Transmission Line Pulse (TLP)
- Test Standards
- ESDA SP5.5-200
The purpose of TLP is to learn the precise pulse current limit of the device. TLP testing uses a constant impedance transmission line as a pulse source because it can create a constant amplitude rectangular pulse shape. The short TLP pulses are used to simulate the short ESD pulse threats that the input-output (I/O) pins of an IC must withstand without damage being caused to the complex silicon structures.